diff --git a/src/cpu/cpu_table.c b/src/cpu/cpu_table.c index fc6429300..1086f3a56 100644 --- a/src/cpu/cpu_table.c +++ b/src/cpu/cpu_table.c @@ -7306,6 +7306,129 @@ const cpu_family_t cpu_families[] = { .cache_write_cycles = 14, .atclk_div = 54 }, + /* Experimental bus grades for pushing past 450MHz on the P2. + * Crucially the 350-450 MHz timing pattern is maintained, so + * 90 ns memory and 30 ns cache accesses, rounded to the + * nearest CPU cycle (halves up), same 8.33 MHz AT clock though! + * Super experimental <3 nyaa.sh */ + { /* out of spec */ + .name = "500", + .cpu_type = CPU_PENTIUM2D, + .fpus = fpus_internal, + .rspeed = 500000000, + .multi = 5.0, + .voltage = 2050, + .edx_reset = 0x652, + .cpuid_model = 0x652, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 45, + .mem_write_cycles = 45, + .cache_read_cycles = 15, + .cache_write_cycles = 15, + .atclk_div = 60 + }, + { /* out of spec */ + .name = "550", + .cpu_type = CPU_PENTIUM2D, + .fpus = fpus_internal, + .rspeed = 550000000, + .multi = 5.5, + .voltage = 2050, + .edx_reset = 0x652, + .cpuid_model = 0x652, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 50, + .mem_write_cycles = 50, + .cache_read_cycles = 17, + .cache_write_cycles = 17, + .atclk_div = 66 + }, + { /* out of spec */ + .name = "600", + .cpu_type = CPU_PENTIUM2D, + .fpus = fpus_internal, + .rspeed = 600000000, + .multi = 6.0, + .voltage = 2050, + .edx_reset = 0x652, + .cpuid_model = 0x652, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 54, + .mem_write_cycles = 54, + .cache_read_cycles = 18, + .cache_write_cycles = 18, + .atclk_div = 72 + }, + { /* out of spec */ + .name = "650", + .cpu_type = CPU_PENTIUM2D, + .fpus = fpus_internal, + .rspeed = 650000000, + .multi = 6.5, + .voltage = 2050, + .edx_reset = 0x652, + .cpuid_model = 0x652, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 59, + .mem_write_cycles = 59, + .cache_read_cycles = 20, + .cache_write_cycles = 20, + .atclk_div = 78 + }, + { /* out of spec */ + .name = "700", + .cpu_type = CPU_PENTIUM2D, + .fpus = fpus_internal, + .rspeed = 700000000, + .multi = 7.0, + .voltage = 2050, + .edx_reset = 0x652, + .cpuid_model = 0x652, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 63, + .mem_write_cycles = 63, + .cache_read_cycles = 21, + .cache_write_cycles = 21, + .atclk_div = 84 + }, + { /* out of spec */ + .name = "750", + .cpu_type = CPU_PENTIUM2D, + .fpus = fpus_internal, + .rspeed = 750000000, + .multi = 7.5, + .voltage = 2050, + .edx_reset = 0x652, + .cpuid_model = 0x652, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 68, + .mem_write_cycles = 68, + .cache_read_cycles = 23, + .cache_write_cycles = 23, + .atclk_div = 90 + }, + { /* out of spec */ + .name = "800", + .cpu_type = CPU_PENTIUM2D, + .fpus = fpus_internal, + .rspeed = 800000000, + .multi = 8.0, + .voltage = 2050, + .edx_reset = 0x652, + .cpuid_model = 0x652, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 72, + .mem_write_cycles = 72, + .cache_read_cycles = 24, + .cache_write_cycles = 24, + .atclk_div = 96 + }, { .name = "", 0 } } },